Cadence INCISIVE v15.20.001

Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled INCISIVE 15.20.001, the single-kernel verification platform for nanometer-scale designs that supports a unified verification methodology for the embedded software, control, data path, and analog/mixed-signal/RF design domains.

Cadence’s Incisive Formal Verification Platform is a full-featured, property-checking formal verification solution. The Incisive platform provides native support for Verilog, VHDL, SystemC, the SystemC Verification Library, property specification language PSL/Sugar, algorithm development and Analog/Mixed Signal (AMS). It includes a unique combination of high-performance capabilities: an extensive transaction-level environment; fast, unified test generation; and Acceleration-on-Demand.

While Cadence continues to fully support Incisive formal technologies, and it remains available for sale to existing customers, we advise customers to use the JasperGold Formal Verification Platform, which is the leading formal verification solution going forward. Indeed, following the integration of certain Incisive formal technologies with the JasperGold platform (see the press release from June 2015), the JasperGold Formal Verification Platform is the recommended solution in all respects.

Learn how to use Vivado design suite to compile simulation libraries and simulate a design using Cadence Incisive Enterprise simulator
Cadence is a pivotal leader in electronic design and computational expertise, using its Intelligent System Design strategy to turn design concepts into reality. Cadence customers are the world’s most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications.

Product: Cadence INCISIVE
Version: 15.20.001 Base release
Supported Architectures: x86_64
Website Home Page : http://www.cadence.com
Languages Supported: english
System Requirements: Linux *
Size: 9.3 Gb

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