Xilinx Vivado Design Suite 2017.1 HLx Editions Win/Linux-0daytown

Vivado Design Suite HLx 版本 – 加速高层次设计

Vivado® Design Suite通过全新 HLx 版本为基于 IP 的新一代 C/C++ 设计实现了一种新型的超高生产力方法，其中包括：HL System 版本、HL Design 版本以及 HL WebPACK™ 版本。

Vivado HLx 版本可为设计团队提供实现基于 C 的设计、重用优化、IP 子系统重复、集成自动化以及设计收敛加速所需的工具和方法。与 UltraFast™ 高层次生产力设计方法指南相结合，这种特殊组合经过验证，不仅可帮助设计人员以高层次抽象形式开展工作，同时还可促进重复使用，从而可加速生产力。
加速高层次设计
软件定义 IP 生成 – Vivado 高层次综合 (HLS)
基于模块的 IP 和 Vivado IP 集成
基于模型的 DSP 设计和 System Generator for DSP集成
加速验证
Vivado 逻辑仿真器
集成混合语言仿真器
集成 & 独立编程与调试环境
加速验证超过 100 倍，通过 C、 C++ 或 SystemC 以及 Vivado HLS
加速实现
设计实现时间缩短 4 倍
设计密度提升 20%
在低端 & 中档产品中实现高达 3 速度级性能优势，在高端产品中实现 35% 功耗优势

Xilinx Vivado Design Suite 2017.1 HLx Editions | 21.3 Gb

Xilinx, Inc. has released Vivado Design Suite HLx Editions 2017.1. The Vivado HL Design Edition and HL System Edition now support partial reconfiguration. Partial reconfiguration is available for the Vivado WebPACK Edition.

Xilinx partial reconfiguration technology allows you to swap FPGA-based functions in and out of your design on the fly, eliminating the need to fully reconfigure the FPGA and re-establish links. Partial reconfigurability gives you the ability to update feature sets in deployed systems, fix bugs, and migrate to new standards while critical functions remain active. This capability dramatically expands the flexible use of Xilinx All Programmable designs in a truly wide variety of applications.

For example, a detailed article published on the WeChat Web site by Siglent about the company’s new, entry-level SDS1000X-E DSO family—based on a Xilinx Zynq Z-7020 SoC—suggests that the new DSO family’s system design employs the Zynq SoC’s partial-reconfiguration capability to further reduce the parts count and the board footprint: “The PL section has 220 DSP slices and 4.9 Mb Block RAM; coupled with high throughput between the PS and PL data interfaces, we have the flexibility to configure different hardware resources for different digital signal processing.” (See “Siglent 200MHz, 1Gsample/sec SDS1000X-E Entry-Level DSO family with 14M sample points is based on Zynq SoC.”)

In addition, the Vivado 2017.1 release includes support for the Xilinx Spartan-7 7S50 FPGA (Vivado WebPACK support will be in a later release). The Spartan-7 FPGAs are the lowest-cost devices in the 28nm Xilinx 7 series and they’re optimized for low, low cost per I/O while delivering terrific performance/watt. Compared to Xilinx Spartan-6 FPGAs, Spartan-7 FPGAs run at half the power consumption (for comparable designs) and with 30% more operating frequency. The Spartan-7 S50 FPGA is a mid-sized family member with 52,160 logic cells, 2.7Mbits of BRAM, 120 DSP slices, and 250 single-ended I/O pins. It’s a very capable FPGA. (For more information about the Spartan-7 FPGA family, see “Today, there are six new FPGAs in the Spartan-7 device family. Want to meet them?” and “Hot (and Cold) Stuff: New Spartan-7 1Q Commercial-Grade FPGAs go from -40 to +125°C!”)

About Xilinx

Xilinx develops All Programmable technologies and devices, beyond hardware to software, digital to analog, and single to multiple die in 3D ICs.A These industry leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration.

Product: Xilinx Vivado Design Suite
Version: 2017.1 HLx Editions
Supported Architectures: x64
Website Home Page : http://www.xilinx.com
Language: english
System Requirements: PC / Linux
Supported Operating Systems: Windows: 7even / 10 | Linux: Red Hat Enterprise / SUSE Enterprise / Ubuntu / CentOS
Size: 21.3 Gb

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