Synopsys, Inc. has introduced Synopsys Euclide 2020.12 SP1, the industry’s next-generation hardware description language (HDL)-aware integrated development environment (IDE). Synopsys Euclide enables engineers to find bugs earlier and optimize code for design and verification flows by identifying complex design and testbench compliance checks during SystemVerilog and Universal Verification Methodology (UVM) development.
The Synopsys Euclide solution is an integrated development environment intended for chip designers and verification engineers. It helps to cut project time, avoid re-spins, improve code quality, and reduce chip area and power..
Synopsys’ Euclide solution is the only tool featuring on-the-fly incremental compilation, elaboration, pseudo-synthesis and rule checking – all of which are integrated into the editor and provide feedback in seconds. With Euclide’s toolset you can immediately minimalize implementation bugs in design and testbench, thus substantially improving project convergence rate and eliminating patchy code. Designed to be simple and intuitive, the tool offers unparalleled user experience, allows immediate and effortless ramp-up, and ensures a fast learning curve for beginners.
Synopsys, Inc. is the Silicon to Software partner for innovative companies developing the electronic products and software applications we rely on every day. As an S&P 500 company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and offers the industry’s broadest portfolio of application security testing tools and services. Whether you’re a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing more secure, high-quality code, Synopsys has the solutions needed to deliver innovative products.
Product: Synopsys Euclide
Version: 2020.12 SP1
Supported Architectures: x86_64
Website Home Page : http://www.synopsys.com
Languages Supported: english
System Requirements: Linux *
Size: 649.5 mb
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