Intel Quartus Prime Standard/Professional Edition 17.1 Linux

Altera, now part of Intel, announced the production release of the updated version Quartus Prime 17 design software, which further accelerates FPGA design performance and design team productivity.

What’s New in Intel Quartus Prime Design Software 17.1:

Intel Quartus Prime software 17.1 is about supercharging your design with all the new features and capabilities that the Intel Quartus Prime Pro Edition software has to offer. There are improvements made across the three key areas that designers care about the most—performance, productivity, and usability.

Performance

Intel Stratix 10 MX, SX, and GX Device Support

Intel Quartus Prime Pro Edition software 17.1 supports Intel Stratix 10 MX, SX, and GX devices.

– Intel Stratix 10 GX devices are designed to meet the high-performance demands of high-throughput systems with up to 10 TFLOPS of floating-point performance and transceiver support up to 28.3 Gbps for chip-module, chip-to-chip, and backplane applications.
– Intel Stratix 10 SX SoCs feature a hard processor system with a 64 bit quad-core ARM Cortex-A53 processor available in all densities in addition to all the features of Intel Stratix 10 GX devices.
– Intel Stratix 10 MX devices combine the programmability and flexibility of Intel Stratix 10 FPGAs and SoCs with the 3D stacked high-bandwidth memory 2 (HBM2) in a single package. Intel Stratix 10 MX FPGAs support both H- and E- transceiver tiles.

With the revolutionary Intel HyperFlex FPGA Architecture, Intel Stratix 10 devices deliver performance gains over previous-generation high-performance FPGAs.

Intel Quartus Prime Software Hyper-Aware Design Flow and Using Fast Forward Compile for the Intel HyperFlex FPGA Architecture are two updated training classes that you can take to understand the Intel HyperFlex FPGA Architecture specifics.

Productivity

– Intel HLS Compiler
You can now accelerate FPGA development with C++ using the new Intel HLS Compiler. The Intel HLS Compiler is a high-level synthesis (HLS) tool that takes in untimed C++ as input and generates production-quality register transfer level (RTL) code that is optimized for Intel FPGAs. For more details, visit the Intel HLS Compiler web page. Note that the Intel HLS Compiler supports all editions of Intel Quartus Prime software 17.1.
– Improved Block-Based Design Flows
The block-based design flows—Design Block Reuse and Incremental Block-Based Compilation—are now supported in Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 device families. There are new features with each of these flows that are described in the Block-Based Design Flows section in volume 1 of the Intel Quartus Prime Pro Edition Handbook. There is also a new tutorial for the design reuse flow on the block-based design flow homepage.
– Partial Reconfiguration
Partial Reconfiguration allows you to reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function. With Intel Quartus Prime Pro Edition software 17.1, there are three key Partial Reconfiguration features for Intel Stratix 10 and Intel Arria 10 device families:
. Hierarchical partial reconfiguration
. Simulation of partial reconfiguration
. Simultaneous debug of static and dynamic partial reconfiguration regions with the Signal Tap logic analyzer
– Logic Equivalency Checking
Logic Equivalency Checking (LEC) is a new feature supported with the Intel HyperFlex FPGA Architecture in Intel Quartus Prime Pro Edition software 17.1. It proves that the post Intel HyperFlex FPGA Architecture-optimized netlist is equivalent to the post fitter netlist. A third-party tool that you can refer to is the 360-EC FPGA solution by OneSpin.
– Platform Designer (formerly Qsys)
With Intel Quartus Prime Pro Edition software 17.1, you can now add C++ (.cpp) files to the Platform Designer and define intellectual property (IP) components around them. You can also incorporate IP components that use SystemVerilog Interfaces into Platform Designer systems.
– Intel Stratix 10 Device Post-Fit Tap for Faster Debug Iterations
Intel Stratix 10 FPGA designs will now have the ability to change the Signal Tap logic analyzer probe points without re-compilation, resulting in faster debug iterations. Therefore, if only the probes are changing in your design, you do not need to recompile your design and can simply route the probe points, which saves you significant time. Read more in the Design Debugging with the Signal Tap Logic Analyzer section in volume 3 of the Intel Quartus Prime Pro Edition Handbook.
– Design Partition Planner
The Design Partition Planner in Intel Quartus Prime Pro Edition software 17.1 allows you to view design connectivity and hierarchy as well as assist you in creating, optimizing, and gauging the quality of your design partitions. Read more in the Design Partition Guidelines section in volume 1 of the Intel Quartus Prime Pro Edition Handbook.

Usability

– Software Tools on the Cloud
With Intel Quartus Prime Pro Edition software 17.1, you can accelerate your applications using Intel FPGA programming tools on the cloud to program FPGAs in a high-performance computing environment provided by Nimbix. Learn more on the Cloud Services web page.
– Usability Enhancements
Some features have now been enhanced from a usability standpoint in Intel Quartus Prime Pro Edition software 17.1. Some of them are as follows:
. edesigned IP upgrade dialog box
. Logic lock regions. There is a new Chip Planner training class that you can take to understand floorplanning and logic lock regions.

For the full list of new and improved features, and fixed bugs please refer to the release notes located here

About Intel Quartus Prime. The new revolutionary Intel Quartus Prime design software includes everything you need to design for Intel FPGAs, SoCs, and CPLDs from design entry and synthesis to optimization, verification, and simulation. Dramatically increased capabilities on devices with multi-million logic elements, are providing designers with the ideal platform to meet next-generation design opportunities. For designers to effectively take advantage of these devices, software must dramatically increase design productivity. The new Quartus Prime software, built on the successful Quartus II software, is breaking barriers of FPGA design productivity. The Quartus Prime software is available in three editions based on your design requirements:

– Quartus Prime Pro Edition–The Quartus Prime Pro Edition software is optimized to support the advanced features in next-generation FPGAs and SoCs, starting with the Intel Arria® 10 device family.
– Quartus Prime Standard Edition–The Quartus Prime Standard Edition software includes the most extensive support for earlier device families and requires a subscription license.
– Quartus Prime Lite Edition–The Quartus Prime Lite Edition software provides an ideal entry point to high-volume device families and is available as a free download with no license file required.

About Altera Corporation. Altera Corporation is at the forefront of technology innovation, providing customers programmable solutions for leading-edge electronic systems that are shaping our modern world. Headquartered in Silicon Valley, California, Altera has been supplying the industry with access to the latest programmable logic, process technologies, IP cores and development tools for more than 30 years. Altera was founded in 1983 and employs more than 3,000 people in over 20 countries.

Product: Intel Quartus Prime
Version: Standard Editon 17.1.0.590 / Professional Edition 17.1.0.240
Supported Architectures: x64
Website Home Page : http://www.altera.com
Language: english
System Requirements: Linux
Supported Operating Systems: Red Hat Enterprise Linux 5.10, 6.8, 7.3
Size: 8.5 Gb

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