The SSV Release Team has unveiled the Cadence Silicon Signoff and Verification (SSV) 20.20.000. This solution encapsulates a set of tools that address a series of electrical and physical signoff and verification steps that designers must perform on their design before tapeout.
Featured Enhancements
Here is a list of some of the important updates made to Tempus Timing Signoff Solution for the 20.2 production release:
Tempus
Tempus Power Integrity Flow
The Tempus Power Integrity Analysis (Tempus PI) solution provides the capability to run IR analysis that is timing-aware, and timing analysis that is IR-aware. The Tempus PI is a seamless integration of the Tempus static timing analysis (STA) and Voltus power and IR drop technologies.
Infinite Depth Path-Based Analysis (IPBA)
The Tempus software supports infinite depth path-based analysis (IPBA). This feature runs faster analysis (vs full depth exhaustive PBA (EPBA)) and attains PBA design coverage with no depth limit per endpoint.
SmartScope Supports Timing Context Models
The Tempus SmartScope feature allows you to perform timing analysis with block context models – which is a top-down hierarchical STA technique. The context model feature allows block timing/glitch analysis and closure with realistic constraints instead of pessimistic block budgeted constraints.
Large Number of Active Timing Views Using SmartMMMC
The Tempus software provides the ability to handle a large number of active timing views using the SmartMMMC feature. This feature is used to enable reduced memory and faster run time when many timing views are enabled during timing or power ECO fixing stage.
New Metal ECO Flow
A new Metal ECO flow, also called Post-Mask ECO, using the Gate Array filler cells has been introduced. In this flow, the timing closure engine performs the netlist change without touching the base layer mask.
Silicon signoff and verification (SSV) encapsulates a set of tools that address a series of electrical and physical signoff and verification steps that designers must perform on their design before tapeout. These steps report errors that require iterative and incremental fixes, also called engineering change orders (ECOs), ensuring the design integrity from an electrical and physical standpoint. All of Cadence’s signoff tools or capabilities are integrated in the Virtuoso platform, providing the same capabilities for mixed-signal and custom designs.
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Cadence is a pivotal leader in electronic design and computational expertise, using its Intelligent System Design strategy to turn design concepts into reality. Cadence customers are the world’s most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications.
Owner: Cadence
Product Name: Silicon Signoff and Verification (SSV)
Version: 20.20.000 Base Release
Supported Architectures: x86_64
Website Home Page : http://www.cadence.com
Languages Supported: english
System Requirements: Linux *
Size: 5.6 Gb
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