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Cadence PERSPECAGILE 24.03.001 Linux

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Cadence PERSPECAGILE 24.03.001
Cadence Design Systems, Inc.(Cadence 设计系统公司) 全球电子设计创新的领导者,发布了 PERSPEC  ,这是一款便携式激励、片上系统 (SoC) 验证解决方案。
Cadence Perspec System Verifier 是一款强大的工具,可自动生成测试用例。它用 C 语言创建测试用例,这些测试用例可用于各种测试台环境。Perspec 系统验证器可以通过使用适当的抽象级别来有效地验证 SoC 的性能、功能和功耗。它是一个便携式平台,可以在从IP到系统级别的不同范围内重复使用,包括硬件感知软件。这种方法侧重于垂直和水平重用 – 垂直重用涵盖从IP级验证到子系统再到SOC级验证。相比之下,水平重用涉及在虚拟原型平台、仿真、仿真和 FPGA 中使用测试意图。最终,这种方法有助于减少创建测试所花费的时间和精力。PSS 提供了验证意图的单一抽象规范,该规范允许工具为参与验证的各种平台生成特定于目标的测试实现。这使团队可以专注于应该测试的内容,而不是多次实施相同的测试。PSS 还可以通过随机生成受抽象规范中定义的规则和约束约束的场景来自动化该过程,从而最大限度地提高覆盖范围,并确保在多个平台上高效执行各种测试。


Cadence PERSPECAGILE 24.03.001 | 4.1 Gb

Cadence Design Systems, Inc. , the leader in global electronic design innovation, has released PERSPEC 24.03.001 is a portable stimulus, system-on-chip (SoC) verification solution.

Cadence Perspec System Verifier is a robust tool that automates the generation of test cases. It creates test cases in the C language, which can be used with various testbench environments. The Perspec System Verifier can effectively validate SoC’s performance, function, and power by using an appropriate level of abstraction. It is a portable platform that can be reused across different scopes, including hardware-aware software, from IP to the system level. This approach focuses on both vertical and horizontal reuse – vertical reuse covers IP level verification to subsystem to SOC level verification. In contrast, horizontal reuse involves using the test intent across virtual prototype platforms, simulation, emulation, and FPGA. Ultimately, this approach helps to reduce the time and effort spent on creating tests. PSS provides a single abstract specification of verification intent, which allows tools to generate target-specific implementations of the test for the various platforms involved in verification. This frees teams to focus on what should be tested instead of implementing the same test multiple times. PSS can also automate the process by randomly generating scenarios subject to the rules and constraints defined in the abstract specification, maximizing coverage, and ensuring efficient execution of a wide range of tests on multiple platforms.

Verification of your mixed-signal design can be a nightmare, with clashing disciplines and engineering cultures, and challenging use-case requirements. In this episode of Chalk Talk, Amelia Dalton chats with Steve Carlson of Cadence Design Systems about a comprehensive approach to mixed-signal system verification.
Cadence is a pivotal leader in electronic design and computational expertise, using its Intelligent System Design strategy to turn design concepts into reality. Cadence customers are the world’s most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications.

Owner: Cadence Design Systems Inc.
Product Name: PERSPEC Agile
Version: 24.03.001 Base release
Supported Architectures: x86_64
Website Home Page : http://www.cadence.com
Languages Supported: english
System Requirements: Linux *
Size: 4.1 Gb


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