Cadence Design Systems, Inc.（纳斯达克股票代码：CDNS）今天宣布，随着新的生产部署完成，客户对 Cadence Cerebrus Intelligent Chip Explorer 的采用正在加速。鉴于 Cadence Cerebrus 采用人工智能 (AI) 技术来自动化和扩展数字芯片设计，它为客户提供了优化功率、性能和面积 (PPA) 以及提高工程生产力的引人注目的价值主张。
Cadence Cerebrus 是一种变革性的 AI 驱动技术，具有独特的强化学习引擎，可自动优化工具和芯片设计选项，以显着减少工程工作量和总体流片时间来提供更好的 PPA。例如，Cadence Cerebrus 平面图优化功能使客户能够缩小芯片尺寸，使其超出人类的设计潜力。因此，Cadence Cerebrus 与更广泛的 Cadence 数字产品组合相结合，通过业界最先进的数字全流程（从综合到实施和签核）提供了突破性的工程优势。
“我们一直在寻找新的方法来帮助我们的客户提高生产力，Cadence Cerebrus 通过其 AI 功能最大限度地减少人工工作，因此设计工程师可以专注于更关键的项目，”高级副总裁 Chin-Chi Teng 博士说和 Cadence 数字与签核集团总经理。“我们在不到一年前推出了 Cadence Cerebrus，看到我们的客户以如此之快的速度启动和运行并开始实现产品的全部潜力，这是非常了不起的。像联发科和瑞萨这样的客户已经看到了如此积极的 PPA 和生产力结果，他们现在已经在生产流程中广泛采用了该工具。”
联发科生产采用
联发科技是一家领先的无晶圆半导体公司，其产品每年为超过 20 亿台移动、智能家居、连接和 AIoT 产品的连接设备提供动力。
联发科硅产品开发高级总经理 Harrison Hsieh 表示：“在联发科，我们决心提供最佳 PPA，使基于 Cadence Cerebrus 人工智能的解决方案成为我们最新的高级节点项目最合乎逻辑的选择。” “在 SoC 模块上，Cadence Cerebrus 布局规划优化功能将芯片面积缩小了 5%，并将功耗降低了 6% 以上。在体验了提高生产力、更好的 PPA 以及易于集成到 MediaTek CAD 流程的综合优势之后，我们在我们的生产流程中部署了 Cadence Cerebrus。”
瑞萨电子产品采用
瑞萨电子是为汽车、工业、基础设施和物联网行业提供微控制器、模拟和电源设备的领先供应商。
瑞萨电子公司共享研发 EDA 部门的副总裁 Toshonori Inoshita 表示：“我们需要能够改进各种节点和设计类型的 PPA 的自动化方法。” “通过部署和优化 Cadence Cerebrus 来满足我们所有的独特需求，我们已经取得了许多显着的设计胜利。在高级节点 CPU 设计中，我们体验到了更好的性能，总负松弛 (TNS) 提高了 75%。此外，Cadence Cerebrus 大幅降低了关键 MCU 设计的泄漏功率。我们希望通过 Cadence Cerebrus 进一步提高性能和生产力，并缩短流片时间。”
Cadence Cerebrus是Cadence数字全流程的一部分，包括Innovus实现系统、Genus综合解决方案和TempusÔ时序签核解决方案，并支持Cadence智能系统设计策略，使客户能够实现SoC设计的卓越。有关 Cerebrus 的更多信息，请访问 http://www.cadence.com/go/cerebrucspr。
Cadence Design Systems, Inc., the leader in global electronic design innovation, has unveiled Cerebrus 23.10.000 is a revolutionary, machine learning-driven, automated approach to chip design flow optimization.
General Access Features delivered in Cerebrus 23.10.000
– Improved robustness of Re-baseline (using Scenario Replay in base flow) + Exploration (with or without -in_models)
– Ability to restart in a new path without moving the data
– Non-standard flow phases are made ignore_cost by default
– FPOPT support for designs without macro
– Command to compress scenario manually
– Default weight for dynamic/internal power set same as leakage
– Ctrl-C handling: Exit only when Cerebrus master is waiting
– Support for file based licensing and GUI (instead of http)
Early Access Features available in Cerebrus 23.10.000
– Automatically costing synthesis earlier than prects when ispatial not used
– New Fast mode option to adaptively handle PPA – TAT tradeoff
– Updates to CTS App to explore Clock tree parameters
Other recent updates (also back ported to Cerebrus 22.1x)
– CTS-postCTS, and Route-Postroute Flow Phases Combined for Costing
– Hold Cost enabled by default
– Combining Multiple Input Models into a Unified Output Model Feature
– Ignoring costing of non-standard flow phases automatically
– Exploring Margins Optimizer and PPA Primitives Concurrently
– Early Termination Based on Percentage of Base Scenario Metric Values
– WNS(100) Metric Made Default
Cadence Cerebrus is a transformational AI-driven technology that has a unique reinforcement learning engine, which automatically optimizes tool and chip design options to deliver better PPA with significantly less engineering effort and overall time to tapeout. As one example, the Cadence Cerebrus floorplan optimization feature enables customers to shrink the die size beyond a human’s design potential. As a result, Cadence Cerebrus, when coupled with the broader Cadence digital product portfolio, provides a breakthrough engineering benefit with the industry’s most advanced digital full flow, from synthesis through implementation and signoff. Cadence Cerebrus is part of the Cadence digital full flow, which includes the Innovus Implementation System, Genus Synthesis Solution and Tempus Timing Signoff Solution, and supports the Cadence Intelligent System Design strategy, enabling customers to achieve SoC design excellence.
Venkat Thanvantri, VP of Machine Learning R&D, describes the innovative distributed computing and reinforcement learning technology that enables Cadence Cerebrus Intelligent Chip Explorer to deliver better PPA more quickly. Cerebrus, the Future of Intelligent Chip Design.
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work
Owner: Cadence Design Systems, Inc.
Product Name: Cerebrus
Version: 23.10.000 Base Release (Feburary 02, 2024)
Supported Architectures: x86_64
Website Home Page : http://www.cadence.com
Languages Supported: english
System Requirements: Linux *
Size: 1.6 Gb
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