Xilinx Vivado Design Suite HLx Editions 2016.4 Win/Linux

Vivado Design Suite HLx 版本 – 加速高层次设计

Vivado® Design Suite通过全新 HLx 版本为基于 IP 的新一代 C/C++ 设计实现了一种新型的超高生产力方法，其中包括：HL System 版本、HL Design 版本以及 HL WebPACK™ 版本。

Vivado HLx 版本可为设计团队提供实现基于 C 的设计、重用优化、IP 子系统重复、集成自动化以及设计收敛加速所需的工具和方法。与 UltraFast™ 高层次生产力设计方法指南相结合，这种特殊组合经过验证，不仅可帮助设计人员以高层次抽象形式开展工作，同时还可促进重复使用，从而可加速生产力。
加速高层次设计
软件定义 IP 生成 – Vivado 高层次综合 (HLS)
基于模块的 IP 和 Vivado IP 集成
基于模型的 DSP 设计和 System Generator for DSP集成
加速验证
Vivado 逻辑仿真器
集成混合语言仿真器
集成 & 独立 编程与调试环境
加速验证超过 100 倍，通过 C、 C++ 或 SystemC 以及 Vivado HLS
加速实现
设计实现时间缩短 4 倍
设计密度提升 20%
在低端 & 中档产品中实现高达 3 速度级性能优势，在高端产品中实现 35% 功耗优势

Xilinx Vivado Design Suite HLx Editions 2016.x | 21.2 Gb

Xilinx, Inc. has released update for Vivado Design Suite HLx Editions 2016, enabling a new ultra high productivity approach for designing All Programmable SoCs, FPGAs, and the creation of reusable platforms. 

These new HLx Editions include HL System Edition, HL Design Edition and HL WebPACK Edition. All HLx Editions include Vivado High-Level Synthesis (HLS) including C/C++ libraries, Vivado IP Integrator (IPI), LogicCORE IP subsystems, and the full Vivado implementation tool suite to enable mainstream users to readily adopt the most productive and advanced C and IP-based design flows. When coupled with the new UltraFast High-Level Productivity Design Methodology Guide, users can realize a 10-15X productivity gain over traditional approaches. The HLx Edition is available as a no-cost upgrade to the Vivado Design Suite.

Ultra High Productivity for Creating and Programming Reusable Platforms

Over the last 4 years, leading edge Xilinx customers have pioneered and matured the enabling C and IP-based design technologies and methodologies now included in the HLx Editions, and proven the 10-15X productivity potential. To realize this productivity, these customers adopted all or a subset of the following;

– C-based design and optimized reuse,
– reuse of IP subsystems,
– integration automation, and accelerated design closure.

Unlike tradition RTL-based design where the majority of the design effort is spent in the backend of the design process, C and IP-based design enables vastly superior design reuse to speed creation, rapid design exploration for better micro-architectures, replaces error prone manual C to RTL conversion, eliminates time and errors while integrating C and RTL-based IP, and dramatically shortens verification time. Using high levels of abstraction, customers have found that they can quickly get overall better or equal Quality of Results (performance, power, utilization).

To enable these high productivity flows, the HLx Editions include Vivado HLS, Vivado IPI, LogicCORE IP subsystems, and the full Vivado implementation tool suite. In addition, Xilinx and its Alliance ecosystem are continuously expanding market-specific C libraries such as OpenCV for video and image processing and Machine Learning for Automotive Driver Assistance Systems (ADAS) and Data Center applications. Xilinx’s new LogiCORE IP subsystems are highly configurable, market-tailored building blocks that integrate up to 80 individual IP cores, software drivers, design examples, and test benches. New IP subsystems are available for Ethernet, PCIe, video processing, image sensor processing, and OTN development. These IP subsystems are based on industry standards such as AMBA AXI 4 interconnect protocol, IEEE P1735 encryption and IP-XACT to enable interoperability with Xilinx and Alliance member IP and to accelerate integration.

The combination of C-based IP and pre-packaged IP subsystems are rapidly combined leveraging Vivado IP Integrator for integration automation. Vivado IPI’s integration automation provides a device and platform aware, interactive environment that supports intelligent auto-connection of key IP interfaces, one-click IP subsystem generation, real-time DRCs, and interface change propagation, combined with a powerful debug capability. The platform aware intelligence, can preconfigure the Zynq SoCs and MPSoCs processing system with the correct peripherals, drivers, and memory map to support the target board. Design teams can now rapidly identify, reuse, and integrate both software and hardware IP, targeting the ARM processing systems and high-performance FPGA logic.

HLx Complements SDx for Creating and Deploying Platforms

HLx speeds the creation, modification, and programming of All Programmable platforms for hardware engineers, complementing the Xilinx SDx Development Environments (SDSoC, SDAccel and SDNet) which are tailored for software and systems engineers. The SDx family of development environments enable software-defined programming of HLx generated platforms using a mix of C, C++, OpenCL, and the emerging P4 language for packet processing. HLx and SDx represent Xilinx’s new era of design enablement solutions for developing smarter, connected and differentiated systems leveraging a new era of All Programmable devices including Zynq SoCs, MPSoCs, ASIC-class FPGAs and 3D ICs.

Release notes: HERE

About Xilinx

Xilinx develops All Programmable technologies and devices, beyond hardware to software, digital to analog, and single to multiple die in 3D ICs. These industry leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration.

Product: Xilinx Vivado Design Suite HLx Editions
Version: 2016.3
Supported Architectures: 64bit
Website Home Page : http://www.xilinx.com
Language: english
System Requirements: PC / Linux
Supported Operating Systems: Windows 7even / 8.x / 10 | Red Hat Enterprise Workstation/Server 7.1 and 7.2 / Red Hat Enterprise Workstation 6.7 and 6.8 / Red Hat Enterprise Workstation 5.11 / SUSE Linux Enterprise 11.4 and 12.1 / Cent OS 6.8 / Ubuntu Linux 16.04 LTS
Size: 21.2 Gb

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