Xilinx Vivado Design Suite 2014.3 ISO-TBE-0daytown

Vivado Design Suite 2014.4 提升生产力

最新版 Vivado® Design Suite 扩展了对 Virtex UltraScale™ 器件的支持，对 7 系列器件提升了 20% 的编译时间，总体性能提升包括：

Vivado 高层次综合 (HLS) 提升了结果质量，其中 fmax 提升了10%， LUT 利用率改善了 5%，并且 AMBA AXI-4 接口推断也得以改进。
Vivado IP Integrator提供了下一层次的设计辅助，包含流与存储映射 AXI 互连之间的连接自动化，并扩展至 Vivado IP Catalog。

Vivado® Design Suite 提供全新构建的SoC 增强型、以 IP 和系统为中心的下一代开发环境，以解决系统级集成和实现的生产力瓶颈 Vivado Design suite在总体生产力、使用简易性和系统级集成能力方面领先一代。

加速实现
- 设计实现时间缩短 4 倍
- 设计密度提升 20%
- 高达 3 速度级性能优势; 功耗降低 35%
加速集成
- 基于C 的 IP 和 VIVADO HLS
  集成
- 基于模型的 DSP 设计和 System Generator for DSP
  集成
- 基于模块的 IP 和 VIVADO IP Integrator 集成
加速验证
- 面向设计和仿真的集成设计环境
- 全面的硬件调试
- 使用 C、 C++ 或 SystemC 加速验证超过 100 倍

Xilinx Vivado Design Suite 2014.4 | 5.17 GB

The Vivado® Design Suite delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. The Vivado Design suite is a Generation Ahead in overall productivity, ease-of-use, and system level integration capabilities.

Accelerating Implementation:
4X Faster Implementation
20% Better Design Density
Up to 3-Speedgrade Performance Advantage and 35% Less Power

Accelerating Integration:
C-based IP Generation with Vivado High Level Synthesis
Model-based DSP Design Integration with System Generator for DSP
Block-based IP Integration with Vivado IP Integrator

Accelerating Verification:
Integrated Design Environment for Design and Simulation
Comprehensive Hardware Debug
Accelerate Verification by >100X with C, C++ or SystemC

Note: SDK is included!

What’s New:
Vivado Design Suite 2014.3 Accelerates Your Productivity
The latest release of the Vivado® Design Suite features expanded support for Virtex UltraScale™ devices, 20% compile time improvements for 7 series devices and overall performance improvements including:
Vivado High-Level Synthesis includes enhancements to quality-of-results with an average of 10% better fmax and 5% lower LUT utilization and along with AMBA AXI-4 interface inference
Vivado IP Integrator provides the next level of design assistance with the automation of the connectivity between streaming and memory mapped AXI interconnects and extensions to the Vivado IP Catalog

vivado release notes install license: Here

Homepage: Here

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