Genre: eLearning | MP4 | Video: h264, 1280×720 | Audio: aac, 44100 Hz
Language: English | SRT | Size: 1.80 GB | Duration: 5h 36m
What you’ll learn
Creating Custom AXI Lite Interface
Handling Interrupts with Custom AXI Lite Interface
Creating Custom AXI Stream Interface with Vivado Template
Creating Custom AXI Stream Interface with Verilog RTL
Writing Drivers for Custom AXI Interface
Interfacing of Custom AXI Interface with Zynq devices
Requirements
Fundamentals of Xilinx Drivers and Embedded Design Flow
Description
Sometimes the IP’s and the peripheral resources available with Zynq devices are not enough to match performance, functionality requirements which are growing day by day. This opens up a door to develop a custom peripheral / Core / Hardware accelerator with Verilog RTL and integrate them with ZYNQ device with World popular Industry defacto standard viz. AXI Interface. This course will cover steps to build up AXI lite and AXI stream interfaces onto RTL to quickly build Cores ready to communicate with ZYNQ. Welcome to Part 2 of the Embedded Design Series with Zynq FPGA’s and Vivado.
Who this course is for:
Anyone wish to build expertise in designing Custom AXI interface for Zynq Devices
Developing Hardware Accelerators with Verilog RTL
Password/解压密码0daydown
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