Cadence SSV Release Version 22.11.100

The SSV Release Team has unveiled the Cadence Silicon Signoff and Verification (SSV) 22.10.000. This solution encapsulates a set of tools that address a series of electrical and physical signoff and verification steps that designers must perform on their design before tapeout.

Featured Enhancements
Here is a list of some of the important updates made to Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution for the 22.1 production release:

Tempus

Aging-Aware STA Analysis
Semiconductor device performance degrades over time due to various physical phenomena, such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), and process node/device failures. The major factors responsible for device degradation are stress duration, temperature, supply voltage, and logic conditions. Traditionally, timing margins are used for accounting for aging-related timing degradation. The Tempus advanced aging-aware timing analysis addresses aging-related effects accurately, minimizes margins, and improves the PPA (power, performance, and area) of a design.
Inter Power Domain (IPD) Analysis
An increase in the number of power domains in a design has become a challenging aspect for designers. This has resulted in a significant increase in the number of timing signoff corners due to cross combinations of voltage corners. This also leads to long cycle times and large compute requirements for timing signoff. To reduce the cycle time and computation requirements, Tempus provides the new capability to run inter-power domain (IPD) analysis, where only IPD logic in the design will be analyzed, and the timing reports will generate data for the relevant IPD logic only. The reduced capacity requirement per IPD run helps to analyze the IPD logic of the design efficiently.
Via Variation Flow
The statistical via variation feature allows you to define the sensitivity of via resistance as a function of area. Tempus computes the interconnect variation based on statistical via resistance. To support the via variation flow, additional data for modeling via variation is required. This includes via variation side file that contains look-up tables of via resistance statistical data and the extend SPEF file that contains via resistance layer and area information. Tempus timing reports show interconnect variation in the results when via variation is enabled.

Voltus

Performance and Capacity Enhancements
The following enhancements have been made to increase the performance and capacity and provide a better user experience for large designs:
– Support for localized disk data caching to retrieve information quickly and speed up the processing time
– Enhanced capacity for die-model generation by using the advanced Model Order Reduction (MOR) techniques
– Improved the method for fracturing Non-Manhattan shapes, enabling current-aware modeling of the shapes
– Enhanced algorithm for hierarchical net-tracing in designs with many hierarchies
Simplified Use Model for Power Analysis Flows
A new seamless unified solution, “Event-Based Power Analysis,” has been introduced to support multiple power analysis flows simultaneously. In this model, the tool performs accurate state-based power estimation for all events of a scenario in a design. Event-Based Power Analysis is applicable to all event-based vectors, such as VCD, FSDB, SHM, and PHY. The use model for event-based power analysis is: set_power_analysis_mode -method event_based.
New Smart Windows Feature
Voltus introduces the new smart window feature for extracting peak power scenarios from a vector-based activity file. The smart window is a variable size window that enables designers to capture maximum regions of high power dissipation.
Support for Multi-Die Self-Heating Effect Flow
Voltus now supports the multi-die Self-Heating Effect (SHE) analysis flow to understand the effect of temperature variations in gate-level designs. Previously, the SHE flow was supported only in the single-die mode using the analyze_self_heat command.

Silicon signoff and verification (SSV) encapsulates a set of tools that address a series of electrical and physical signoff and verification steps that designers must perform on their design before tapeout. These steps report errors that require iterative and incremental fixes, also called engineering change orders (ECOs), ensuring the design integrity from an electrical and physical standpoint. All of Cadence’s signoff tools or capabilities are integrated in the Virtuoso platform, providing the same capabilities for mixed-signal and custom designs.

Learn about the latest Cadence offerings and solutions directly from our developers and experts. View interesting videos covering feature demos, troubleshooting information, flow launches, and more.
Cadence is a pivotal leader in electronic design and computational expertise, using its Intelligent System Design strategy to turn design concepts into reality. Cadence customers are the world’s most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications.

Owner: Cadence
Product Name: Silicon Signoff and Verification (SSV)
Version: 22.10.000 (Base Release) – 22.11.100-ISR1 *
Supported Architectures: x86_64
Website Home Page : http://www.cadence.com
Languages Supported: english
System Requirements: Linux **
Size: 23.6 Gb

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