Cadence MVS 15.20.000

Cadence MVS 15.20.000 | 522.1 mb

Cadence Design Systems, Inc., the leader in global electronic design innovation, has released 15.20 version of MVS. This release includes the following build versions of LPA, LEA, and CCP. 

Perform all of your electrical verification tasks in an integrated, easy-to-use environment, spanning front-end to back-end design handoff to signoff-driven implementation to final signoff convergence. With high precision, our technologies analyze timing with variation and noise, power consumption, IR drop, electromigration, and thermal characteristics.

Cadence Litho Physical Analyzer (LPA) detects and corrects lithography hotspots, and does so quickly, based on either fast, accurate silicon contour prediction, or high-performance pattern matching.
Litho Physical Analyzer detects manufacturability issues missed by traditional physical verification. Depending on the foundry enablement, the tool can either perform a pattern-based check or use a simulation engine to meet foundry litho requirements. Litho Physical Analyzer not only provides foundry-certified fast-litho detection for signoff, it also allows hotspots to be detected during implementation through tight integration with custom and digital implementation platforms. The solution provides fixing guidelines to increase automated fixing rates.
In addition to litho checks, Litho Physical Analyzer can perform pattern-based layout optimization to improve design quality, increase usage of DFM rules, and automate the fixing of complex design rules.

The Cadence LDE Electrical Analyzer (LEA) helps designers identify, analyze, and minimize the effect of parametric issues associated with manufacturing variability to improve design performance.
LDE Electrical Analyzer is a complete and silicon-correlated electrical design-for-manufacuring (DFM) analyzer that allows you to optimize and control the impact of layout-dependent effects (LDEs), such as stress or well proximity effects (WPEs), on design performance. This tool plugs directly into your existing flows for custom analog, IP, and cell-based digital designs, helping you accelerate timing closure.

Cadence CMP Predictor (CCP) predicts the Chemical and Mechanical Polishing (CMP) variations and their potential impact on your design for the entire layer stack. It turns the uncertainty of manufacturing process variation into predictable impacts, and then minimizes these impacts during the design stage to greatly enhance overall design performance and yield, at the chip level and also at IP level with CCP unique block-based methodology. CMP predictor allows silicon calibration of semi-physical models and optimization of CMP material and process parameters. CMP Predictor provides full-chip, multi-level thickness and topography predictions for the entire stack, covering FEOL, MEOL, BEOL, dielectric deposition, copper electrochemical deposition (ECD), etch depth, and copper/dielectric planarization processes.
CMP-related hotspots, such as copper pooling, can have detrimental effects on chip yield. The conventional rules-based approach to hotspot detection fails to capture long-range and multi-level CMP effects. CMP Predictor uses a highly accurate model-based approach to finding potential hotspot areas. It also feeds the thickness and topography variation data into extraction tools, enabling better RC and timing analysis.
Cadence CMP Predictor integrates with Cadence Virtuoso Layout Suite, Cadence Innovus Implementation System and interfaces closely with the Cadence Quantus QRC Extraction Solution for a complete silicon signoff solution.

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.

Product: Cadence MVS
Version: 15.20.000 Base release
Supported Architectures: x86
Website Home Page : http://www.cadence.com
Language: english
System Requirements: Linux
Supported Operating Systems: RHEL 5.5, RHEL 5.10, RHEL 6.5, RHEL 7.1, SLES 11, SLES 12
Size: 522.1 mb

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