Cadence Allegro and OrCAD (Including EDM) 17.20.007-2016 Linux

Cadence Allegro and OrCAD (Including EDM) 17.20.007-2016 Linux | 1.2 Gb
Cadence Design Systems, Inc. announced new capabilities for OrCAD Capture, PSpice Designer and PCB Designer 17.2-2016 that address challenges with flex and rigid-flex design as well as mixed-signal simulation complexities in IoT, wearables and wireless mobile devices. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.

This OrCAD portfolio includes technology enabled for integrated rigid-flex planning, design and real-time visualization, as well as built-in translators that enable direct design imports from select EDA vendors. PSpice Designer now supports system-level simulation using C/C++/SystemC and VerilogA, via the new PSpice compact model interface. This enables hardware/software virtual prototyping so that electrical engineers can design and simulate intelligent IoT devices. OrCAD is the only fully scalable PCB design solution available in the market that seamlessly transitions from mainstream to enterprise PCB solution with the Allegro environment. For more information on the latest OrCAD solution, visit: HERE

To enable a faster and more efficient flex and rigid-flex design creation critical to IoT, wearables and wireless devices, the OrCAD portfolio uses a new multi-stack-up database capability and extensive in-design inter-layer checks, which helps users avoid errors introduced through manual checking. The OrCAD portfolio also features enhancements targeted towards improving PCB editors’ productivity and ease-of-use in padstack editing, constraint management, shape editing and in-design DRCs. To address efficiency needs, the portfolio includes an advanced design differencing engine that enables design review with global teams using state of art visuals. Finally, to give designers more control over their design component annotation process, advanced annotation and auto-referencing capabilities are now available.

The Cadence Allegro 17.2-2016 release enables a more predictable and shorter design cycle. The portfolio features comprehensive in-design inter-layer checking technology that minimizes design-check-redesign iterations and a new dynamic concurrent-team-design capability that accelerates product creation time by up to 50 percent. Utilizing material inlay fabrication techniques, these new capabilities can reduce material costs by up to 25 percent. In addition, embedded Sigrity technology now ensures critical signals meet performance criteria and power integrity (PI) for PCB designers addressing power delivery and IR drop issues efficiently, eliminating time-consuming iterations with PI experts. For more information on the latest Allegro, visit: HERE

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